PHY_28NM_HSIC_PLL_CTRL2
writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) &
base + PHY_28NM_HSIC_PLL_CTRL2);
writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) |
base + PHY_28NM_HSIC_PLL_CTRL2);
ret = wait_for_reg(base + PHY_28NM_HSIC_PLL_CTRL2,