PHYSICAL_PAGE_MASK
#define PTE_PFN_MASK ((pteval_t)PHYSICAL_PAGE_MASK)
#define CR3_ADDR_MASK __sme_clr(PHYSICAL_PAGE_MASK)
phys_addr &= PHYSICAL_PAGE_MASK;
unsigned long pa = __pa(pgtbl) & PHYSICAL_PAGE_MASK;
pa = pmd_val(*pmd) & PHYSICAL_PAGE_MASK;
pa = pud_val(*pud) & PHYSICAL_PAGE_MASK;
pa = p4d_val(*p4d) & PHYSICAL_PAGE_MASK;
#define PAGE_MASK (~(PAGE_SIZE-1) & PHYSICAL_PAGE_MASK)
#define HUGEPAGE_MASK(x) (~(HUGEPAGE_SIZE(x) - 1) & PHYSICAL_PAGE_MASK)
#define PTE_GET_PA(pte) ((pte) & PHYSICAL_PAGE_MASK)
*pte |= PTE_HUGE_MASK(mmu) | (paddr & PHYSICAL_PAGE_MASK);
*pte |= vm_alloc_page_table(vm) & PHYSICAL_PAGE_MASK;
PTE_ALWAYS_SET_MASK(mmu) | (paddr & PHYSICAL_PAGE_MASK);
pdpe_start = addr_gpa2hva(vm, *pml4e & PHYSICAL_PAGE_MASK);
pde_start = addr_gpa2hva(vm, *pdpe & PHYSICAL_PAGE_MASK);
pte_start = addr_gpa2hva(vm, *pde & PHYSICAL_PAGE_MASK);
TEST_ASSERT((vmx->eptp_gpa & ~PHYSICAL_PAGE_MASK) == 0,
pml5_pa = get_cr3() & PHYSICAL_PAGE_MASK;
pml4_pa = pml5[0] & PHYSICAL_PAGE_MASK;