drivers/net/phy/microchip_t1.c

1069

rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,

drivers/net/phy/microchip_t1.c

371

if (mode > PHYACC_ATTR_MODE_WRITE || bank > PHYACC_ATTR_BANK_MAX)

drivers/net/phy/microchip_t1.c

375

if (mode == PHYACC_ATTR_MODE_WRITE)

drivers/net/phy/microchip_t1.c

382

if (mode == PHYACC_ATTR_MODE_WRITE) {

drivers/net/phy/microchip_t1.c

423

rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, bank, offset, new);

drivers/net/phy/microchip_t1.c

470

return access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,

drivers/net/phy/microchip_t1.c

502

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE,

drivers/net/phy/microchip_t1.c

505

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,

drivers/net/phy/microchip_t1.c

511

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

513

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

515

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

517

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

519

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

521

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

527

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

530

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

532

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

535

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

537

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

539

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

542

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

545

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

547

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

549

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

551

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

553

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

555

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

557

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

559

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

561

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

563

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

565

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

567

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

569

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

571

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

573

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

575

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

577

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

579

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

581

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

583

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

585

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

587

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

589

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

591

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

593

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

595

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

597

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

599

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

601

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

603

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

605

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

607

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

609

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

611

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

613

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

615

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

618

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

621

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

624

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

627

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,

drivers/net/phy/microchip_t1.c

632

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,

drivers/net/phy/microchip_t1.c

635

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,

drivers/net/phy/microchip_t1.c

638

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,

drivers/net/phy/microchip_t1.c

644

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE,

drivers/net/phy/microchip_t1.c

653

{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,

drivers/net/phy/microchip_t1.c

703

rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,

drivers/net/phy/microchip_t1.c

722

rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,

drivers/net/phy/microchip_t1.c

734

rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,

drivers/net/phy/microchip_t1.c

817

{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 93,

drivers/net/phy/microchip_t1.c

820

{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94,

drivers/net/phy/microchip_t1.c

823

{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 95,

drivers/net/phy/microchip_t1.c

826

{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 92,

drivers/net/phy/microchip_t1.c

829

{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 79,

drivers/net/phy/microchip_t1.c

835

{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94,

drivers/net/phy/microchip_t1.c

838

{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 90,

drivers/net/phy/microchip_t1.c

995

rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,