Symbol: PHYACC_ATTR_BANK_DSP
drivers/net/phy/microchip_t1.c
1070
PHYACC_ATTR_BANK_DSP, T1_COEF_RW_CTL_CFG, 0x0301);
drivers/net/phy/microchip_t1.c
1075
PHYACC_ATTR_BANK_DSP, T1_DCQ_SQI_REG, 0x0);
drivers/net/phy/microchip_t1.c
349
if (bank != prev_bank && bank == PHYACC_ATTR_BANK_DSP) {
drivers/net/phy/microchip_t1.c
511
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
513
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
515
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
517
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
519
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
521
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
527
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
530
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
532
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
535
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
537
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
539
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
542
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
545
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
547
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
549
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
551
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
553
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
555
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
557
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
559
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
561
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
563
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
565
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
567
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
569
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
571
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
573
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
575
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
577
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
579
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
581
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
583
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
585
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
587
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
589
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
591
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
593
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
595
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
597
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
599
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
601
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
603
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
605
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
607
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
609
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
611
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
613
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
615
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
618
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
621
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
624
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
627
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
629
{ PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
817
{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 93,
drivers/net/phy/microchip_t1.c
820
{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94,
drivers/net/phy/microchip_t1.c
823
{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 95,
drivers/net/phy/microchip_t1.c
826
{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 92,
drivers/net/phy/microchip_t1.c
829
{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 79,
drivers/net/phy/microchip_t1.c
832
{PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_DSP, 55,
drivers/net/phy/microchip_t1.c
835
{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94,
drivers/net/phy/microchip_t1.c
838
{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 90,
drivers/net/phy/microchip_t1.c
929
PHYACC_ATTR_BANK_DSP, 151, 0);
drivers/net/phy/microchip_t1.c
932
PHYACC_ATTR_BANK_DSP, 153, 0);
drivers/net/phy/microchip_t1.c
934
PHYACC_ATTR_BANK_DSP, 154, 0);
drivers/net/phy/microchip_t1.c
936
PHYACC_ATTR_BANK_DSP, 156, 0);
drivers/net/phy/microchip_t1.c
938
PHYACC_ATTR_BANK_DSP, 157, 0);
drivers/net/phy/microchip_t1.c
988
rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
996
PHYACC_ATTR_BANK_DSP,