PHYACC_ATTR_BANK_DSP
PHYACC_ATTR_BANK_DSP, T1_COEF_RW_CTL_CFG, 0x0301);
PHYACC_ATTR_BANK_DSP, T1_DCQ_SQI_REG, 0x0);
if (bank != prev_bank && bank == PHYACC_ATTR_BANK_DSP) {
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
{ PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP,
{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 93,
{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94,
{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 95,
{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 92,
{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 79,
{PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_DSP, 55,
{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94,
{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 90,
PHYACC_ATTR_BANK_DSP, 151, 0);
PHYACC_ATTR_BANK_DSP, 153, 0);
PHYACC_ATTR_BANK_DSP, 154, 0);
PHYACC_ATTR_BANK_DSP, 156, 0);
PHYACC_ATTR_BANK_DSP, 157, 0);
rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP,
PHYACC_ATTR_BANK_DSP,