PHASE_COMMON
bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);