PHASE28_WM_CS
PHASE28_SPI_CLK|PHASE28_WM_CS));
phase28_spi_write(ice, PHASE28_WM_CS, (reg << 9) | (val & 0x1ff), 16);
snd_ice1712_gpio_set_mask(ice, ~(PHASE28_WM_RESET|PHASE28_WM_CS|
tmp |= PHASE28_WM_CS;