PCLK_UART7
GATE(PCLK_UART7, "pclk_uart7", "pclk_vpu_root", 0,
GATE(PCLK_UART7, "pclk_uart7", "pclk_peri", 0,
GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 0,
GATE(PCLK_UART7, "pclk_uart7", "pclk_bus_root", 0,
GATE(PCLK_UART7, "pclk_uart7", "pclk_top_root", 0,
GATE(PCLK_UART7, "pclk_uart7", "pclk_bus_root", 0,