arch/x86/events/intel/cstate.c

178

[PERF_CSTATE_CORE_C1_RES] = { MSR_CORE_C1_RES, &group_cstate_core_c1, test_msr },

arch/x86/events/intel/cstate.c

475

.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |

arch/x86/events/intel/cstate.c

503

.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |

arch/x86/events/intel/cstate.c

511

.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |

arch/x86/events/intel/cstate.c

523

.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |

arch/x86/events/intel/cstate.c

533

.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |

arch/x86/events/intel/cstate.c

545

.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |

arch/x86/events/intel/cstate.c

564

.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |

arch/x86/events/intel/cstate.c

575

.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |

arch/x86/events/intel/cstate.c

582

.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |