PERF_COUNT_HW_STALLED_CYCLES_BACKEND
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = "bstall",
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 19,
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
[SBI_PMU_HW_STALLED_CYCLES_BACKEND] = PERF_COUNT_HW_STALLED_CYCLES_BACKEND,
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x00d1, /* "Dispatch stalls" event */
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x0187,
case PERF_COUNT_HW_STALLED_CYCLES_BACKEND:
intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
zx_pmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = XTENSA_PMU_MASK(3, 0x1ff),
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6_PERFCTR_LSU_FULL_STALL,
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV7_A9_PERFCTR_STALL_DISPATCH,
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = {.hw_gen_event = {
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = "stalled-cycles-backend",
ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_STALLED_CYCLES_BACKEND)
event_init_opts(&event, PERF_COUNT_HW_STALLED_CYCLES_BACKEND,
event_init_opts(&event, PERF_COUNT_HW_STALLED_CYCLES_BACKEND,