drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c

599

cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c

600

cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c

603

cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c

604

cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c

651

cp_bra (ctx, USER_SAVE, PENDING, cp_exit);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c

182

cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c

183

cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c

186

cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c

187

cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c

209

cp_wait(ctx, INTR, PENDING);

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c

241

cp_bra (ctx, USER_SAVE, PENDING, cp_exit);

drivers/xen/events/events_fifo.c

197

sync_clear_bit(EVTCHN_FIFO_BIT(PENDING, word), BM(word));

drivers/xen/events/events_fifo.c

203

sync_set_bit(EVTCHN_FIFO_BIT(PENDING, word), BM(word));

drivers/xen/events/events_fifo.c

209

return sync_test_bit(EVTCHN_FIFO_BIT(PENDING, word), BM(word));

include/asm-generic/qspinlock_types.h

79

#define _Q_PENDING_MASK _Q_SET_MASK(PENDING)

kernel/signal.c

162

PENDING(&t->pending, &t->blocked) ||

kernel/signal.c

163

PENDING(&t->signal->shared_pending, &t->blocked) ||

tools/testing/selftests/bpf/progs/bpf_arena_spin_lock.h

94

#define _Q_PENDING_MASK _Q_SET_MASK(PENDING)