PCI_PREF_MEMORY_BASE
pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0);
case PCI_PREF_MEMORY_BASE:
pci_write_config_word(dev, PCI_PREF_MEMORY_BASE,
val = dw_pcie_readl_dbi(pci, PCI_PREF_MEMORY_BASE);
dw_pcie_writel_dbi(pci, PCI_PREF_MEMORY_BASE, val);
writel(0x0000fff0, base + PCI_PREF_MEMORY_BASE);
rc = pci_bus_write_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, temp_word);
rc = pci_bus_write_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, temp_word);
pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, &w_base);
pci_bus_read_config_word(ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_BASE, &pfmem_base);
pci_bus_write_config_word(ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_BASE, 0x0000 | bus->rangePFMem->start >> 16);
pci_bus_write_config_word(ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_BASE, 0xffff);
pci_bus_read_config_word(ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_BASE, &start_mem_address);
[PCI_PREF_MEMORY_BASE / 4] = {
bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0;
bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0;
pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);