PCI_INTERRUPT_LINE
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8);
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq_orig);
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
case PCI_INTERRUPT_LINE:
case PCI_INTERRUPT_LINE:
case PCI_INTERRUPT_LINE:
case PCI_INTERRUPT_LINE:
case PCI_INTERRUPT_LINE:
pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 10);
pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 11);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
case (PCI_INTERRUPT_LINE >> 2):
case (PCI_INTERRUPT_LINE >> 2):
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14);
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat);
if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq);
ret = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
rc = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
static const u8 pci_cfg_space_rw_bmp[PCI_INTERRUPT_LINE + 4] = {
[PCI_INTERRUPT_LINE] = 0xff,
pci_write_config_dword(parent, PCI_INTERRUPT_LINE, ddata->bridge_pci_data.interrupt_line);
pci_write_config_dword(pdev, PCI_INTERRUPT_LINE, ddata->bmc_pci_data.interrupt_line);
pci_read_config_dword(parent, PCI_INTERRUPT_LINE, &ddata->bridge_pci_data.interrupt_line);
pci_read_config_dword(pdev, PCI_INTERRUPT_LINE, &ddata->bmc_pci_data.interrupt_line);
(card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) {
(card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) {
dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq);
PCI_INTERRUPT_LINE, 1, irq_pin);
val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
case PCI_INTERRUPT_LINE: {
u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]);
case PCI_INTERRUPT_LINE:
} else if ((where >= PCI_INTERRUPT_LINE && where + size <= PCI_INTERRUPT_PIN) ||
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
case PCI_INTERRUPT_LINE: {
u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]);
case PCI_INTERRUPT_LINE:
writel(0, versatile_cfg_base[0] + PCI_INTERRUPT_LINE);
else if (where == PCI_INTERRUPT_LINE && !(*value & 0xff00))
PCI_INTERRUPT_LINE);
pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &ctrl->cfgspc_irq);
rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_INTERRUPT_LINE, IRQ);
pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_INTERRUPT_LINE, func->irq[irq - 1]);
pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_INTERRUPT_LINE, func->irq[irq - 1]);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
[PCI_INTERRUPT_LINE / 4] = {
bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &=
bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &=
bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &=
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);
pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr);
pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, isp->saved_regs.intr);
p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE);
.offset = PCI_INTERRUPT_LINE,
pci_read_config_dword(pci, PCI_INTERRUPT_LINE, &irq);
pci_write_config_dword(pci, PCI_INTERRUPT_LINE, irq);