PCLK_UART5
GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 9, GFLAGS),
GATE(PCLK_UART5, "pclk_uart5", "pclk_hsperi_root", 0,
GATE(PCLK_UART5, "pclk_uart5", "pclk_vpu_root", 0,
GATE(PCLK_UART5, "pclk_uart5", "pclk_peri", 0,
GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 0,
GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_root", 0,
GATE(PCLK_UART5, "pclk_uart5", "pclk_top_root", 0,
GATE(PCLK_UART5, "pclk_uart5", "pclk_pdbus", 0,
GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_root", 0,