PCLK_UART2
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 6, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 14, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 12, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 13, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_lsperi_root", 0,
GATE(PCLK_UART2, "pclk_uart2", "pclk_vpu_root", 0,
GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0,
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0,
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_root", 0,
GATE(PCLK_UART2, "pclk_uart2", "pclk_top_root", 0,
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0,
GATE(PCLK_UART2, "pclk_uart2", "pclk_pdbus", 0,
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_root", 0,
GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
GATE_BUS(PCLK_UART2, "pclk_uart2", "pclk", PCLK_GATE, 3),
ALIAS(PCLK_UART2, "s3c6400-uart.2", "uart"),