PCLK_UART0
GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 8, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 10, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 11, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 7, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_lsperi_root", 0,
GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0,
GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 0,
GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0,
GATE(PCLK_UART0, "pclk_uart0", "pclk_pmu0_root", 0,
GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", 0,
GATE(PCLK_UART0, "pclk_uart0", "pclk_pdbus", 0,
GATE(PCLK_UART0, "pclk_uart0", "busclk_pmu_root", 0,
GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
GATE_BUS(PCLK_UART0, "pclk_uart0", "pclk", PCLK_GATE, 1),
ALIAS(PCLK_UART0, "s3c6400-uart.0", "uart"),