PCLK_UART1
GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 5, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 13, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 9, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 11, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 12, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 8, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_lsperi_root", 0,
GATE(PCLK_UART1, "pclk_uart1", "pclk_rkvenc_root", 0,
GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0,
GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0,
GATE(PCLK_UART1, "pclk_uart1", "pclk_pmu1_root", 0,
GATE(PCLK_UART1, "pclk_uart1", "pclk_top_root", 0,
GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0,
GATE(PCLK_UART1, "pclk_uart1", "pclk_pdpmu", 0,
GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_root", 0,
GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
GATE_BUS(PCLK_UART1, "pclk_uart1", "pclk", PCLK_GATE, 2),
ALIAS(PCLK_UART1, "s3c6400-uart.1", "uart"),