PCLK_GPIO1
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 8, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 1, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 13, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 8, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "aclk_core_root", 0,
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_vpu_root", 0,
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0,
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_root", 0,
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_top_root", 0,
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0,
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pdbus", 0,
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri_root", 0,