PCLK_GPIO0
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 12, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 7, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3368_CLKGATE_CON(23), 4, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu_root", 0,
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu_root", 0,
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0,
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0,
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0,
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0,