PCI_PM_CTRL_STATE_MASK
if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
dev->current_state = (pci_power_t __force)(pmcsr & PCI_PM_CTRL_STATE_MASK);
& PCI_PM_CTRL_STATE_MASK);
xe_mmio_rmw32(mmio, I2C_CONFIG_PMCSR, PCI_PM_CTRL_STATE_MASK, (__force u32)PCI_D3hot);
xe_mmio_rmw32(mmio, I2C_CONFIG_PMCSR, PCI_PM_CTRL_STATE_MASK, (__force u32)PCI_D0);
csr &= ~PCI_PM_CTRL_STATE_MASK;
csr &= ~PCI_PM_CTRL_STATE_MASK;
((pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
if (pmcsr & PCI_PM_CTRL_STATE_MASK)
pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
(!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
data &= ~PCI_PM_CTRL_STATE_MASK;
if (tmp & PCI_PM_CTRL_STATE_MASK) {
u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
state = pmcsr & PCI_PM_CTRL_STATE_MASK;
dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
csr &= ~PCI_PM_CTRL_STATE_MASK;
csr &= ~PCI_PM_CTRL_STATE_MASK;
if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
d3_state = ((pmcsr & PCI_PM_CTRL_STATE_MASK) ==
switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) {
PCI_PM_CTRL_STATE_MASK));
pwr_cmd = (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | state;
new_state = (__force pci_power_t)(new_value & PCI_PM_CTRL_STATE_MASK);
catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, (__force u32)PCI_D3hot);
catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, (__force u32)PCI_D0);