PCI_LATENCY_TIMER
pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 32);
pci_read_config_byte(dev, PCI_LATENCY_TIMER, <);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 48);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xff);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
eeh_ops->write_config(edev, PCI_LATENCY_TIMER, 1,
SAVED_BYTE(PCI_LATENCY_TIMER));
eeh_ops->write_config(edev, PCI_LATENCY_TIMER, 1,
SAVED_BYTE(PCI_LATENCY_TIMER));
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
grpci1_cfg_w8(priv, TGT, 0, PCI_LATENCY_TIMER, 0x40);
0, PCI_LATENCY_TIMER);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
0, PCI_LATENCY_TIMER);
pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
(reg != PCI_LATENCY_TIMER) &&
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
pci_read_config_byte(pdev, PCI_LATENCY_TIMER, ®);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);
pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &v);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, v);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, latency);
if (pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &timer)) {
if (pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, timer))
result = pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0);
if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) {
(pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0)
pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency);
pci_write_config_byte(pcidev, PCI_LATENCY_TIMER, 32);
pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
pci_write_config_byte(btv->c.pci, PCI_LATENCY_TIMER, latency);
pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &pci_latency);
pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, 64);
pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &pci_latency);
pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
pci_read_config_byte(pci, PCI_LATENCY_TIMER, &pci_lat);
pci_write_config_byte(pci, PCI_LATENCY_TIMER, latency);
pci_read_config_byte(dev->pci, PCI_LATENCY_TIMER, &dev->pci_lat);
pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, latency);
pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, latency);
pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
pci_read_config_byte(zr->pci_dev, PCI_LATENCY_TIMER,
pci_write_config_byte(zr->pci_dev, PCI_LATENCY_TIMER, need_latency);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, IOC3_LATENCY);
pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff);
pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_LATENCY_TIMER, temp_byte);
PCI_LATENCY_TIMER, temp_byte);
pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_LATENCY_TIMER, LATENCY);
pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_LATENCY_TIMER, LATENCY);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpx->latency_timer);
pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
config_writeb(socket, PCI_LATENCY_TIMER, 168);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
pci_read_config_byte(dev, PCI_LATENCY_TIMER, &latency);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, limit);
p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE);
.offset = PCI_LATENCY_TIMER,
pci_read_config_dword(pci, PCI_LATENCY_TIMER, &l_timer);
pci_write_config_dword(pci, PCI_LATENCY_TIMER, l_timer);
pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0xC0);
pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);