PCI_ERR_COR_MASK
pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);
pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);
pci_write_config_dword(root, aer_pos + PCI_ERR_COR_MASK, 0xffff);
case PCI_ERR_COR_MASK:
case PCI_ERR_COR_MASK:
case PCI_ERR_COR_MASK:
case PCI_ERR_COR_MASK:
pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);
pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);
pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask);
pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK,
pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++);
pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++);
pci_read_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK, &cor_mask);
pci_write_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK,
pci_write_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK,
pci_read_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, &val);
pci_write_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, val);
p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask);