ATTENTION_SINGLE
{"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
{"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
{"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
{"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
{"PGLUE config_space", ATTENTION_SINGLE,
{"PGLUE misc_flr", ATTENTION_SINGLE,
{"PGLUE misc_mctp", ATTENTION_SINGLE,
{"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
#define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY)
{"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
{"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
{"General Attention 32", ATTENTION_SINGLE |
{"General Attention 35", ATTENTION_SINGLE |
ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
{"MCP CPU", ATTENTION_SINGLE,
{"MCP Watchdog timer", ATTENTION_SINGLE,
{"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
{"AVS stop status ready", ATTENTION_SINGLE,
{"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS},
{"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE,
{"PERST_B assertion", ATTENTION_SINGLE,
{"PERST_B deassertion", ATTENTION_SINGLE,
{"MCP Latched scratchpad cache", ATTENTION_SINGLE,