AT_WRITE_REG
AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data);
AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
AT_WRITE_REG(hw, REG_OTP_CTRL,
AT_WRITE_REG(hw, REG_EEPROM_DATA_LO, 0);
AT_WRITE_REG(hw, REG_EEPROM_CTRL, control);
AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
AT_WRITE_REG(hw, REG_MDIO_CTRL, 0);
AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
AT_WRITE_REG(hw, REG_MDIO_EXTN, val);
AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
AT_WRITE_REG(hw, REG_MDIO_EXTN, val);
AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data | GPHY_CTRL_EXT_RESET);
AT_WRITE_REG(hw, REG_LPI_CTRL, lpi_ctrl & ~LPI_CTRL_EN);
AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl);
AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl);
AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl);
AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl);
AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl);
AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl);
AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl);
AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
AT_WRITE_REG(hw, REG_PCIE_PHYMISC, data);
AT_WRITE_REG(hw, REG_MASTER_CTRL,
AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
AT_WRITE_REG(hw, atl1c_qregs[i].tpd_addr_lo,
AT_WRITE_REG(hw, REG_TPD_RING_SIZE,
AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI,
AT_WRITE_REG(hw, atl1c_qregs[i].rfd_addr_lo,
AT_WRITE_REG(hw, REG_RFD_RING_SIZE,
AT_WRITE_REG(hw, REG_RX_BUF_SIZE,
AT_WRITE_REG(hw, atl1c_qregs[i].rrd_addr_lo,
AT_WRITE_REG(hw, REG_RRD_RING_SIZE,
AT_WRITE_REG(hw, REG_SRAM_RXF_LEN, 0x02a0L);
AT_WRITE_REG(hw, REG_SRAM_TXF_LEN, 0x0100L);
AT_WRITE_REG(hw, REG_SRAM_RXF_ADDR, 0x029f0000L);
AT_WRITE_REG(hw, REG_SRAM_RFD0_INFO, 0x02bf02a0L);
AT_WRITE_REG(hw, REG_SRAM_TXF_ADDR, 0x03bf02c0L);
AT_WRITE_REG(hw, REG_SRAM_TRD_ADDR, 0x03df03c0L);
AT_WRITE_REG(hw, REG_TXF_WATER_MARK, 0); /* TX watermark, to enter l1 state.*/
AT_WRITE_REG(hw, REG_RXD_DMA_CTRL, 0); /* RXD threshold.*/
AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
AT_WRITE_REG(hw, REG_PCIE_PHYMISC2, data);
AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data);
AT_WRITE_REG(hw, REG_LINK_CTRL, data);
AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
AT_WRITE_REG(hw, REG_MAC_CTRL, data);
AT_WRITE_REG(hw, REG_PM_CTRL, data);
AT_WRITE_REG(hw, REG_TXQ_CTRL, txq);
AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq);
AT_WRITE_REG(hw, REG_MAC_CTRL, mac);
AT_WRITE_REG(hw, REG_DMA_DBG, data & ~DMA_DBG_VENDOR_MSG);
AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data | MASTER_CTRL_SOFT_RST);
AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data);
AT_WRITE_REG(hw, REG_MAC_CTRL, ctrl_data | MAC_CTRL_SPEED_MODE_SW);
AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF);
AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
AT_WRITE_REG(hw, REG_CLK_GATING_CTRL, data);
AT_WRITE_REG(hw, REG_INT_RETRIG_TIMER,
AT_WRITE_REG(hw, REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd);
AT_WRITE_REG(&adapter->hw, REG_MT_MODE, mode);
AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, data);
AT_WRITE_REG(&adapter->hw, atl1c_qregs[queue].rfd_prod,
AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF);
AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT);
AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
AT_WRITE_REG(hw, REG_MASTER_CTRL, mst_data);
AT_WRITE_REG(hw, REG_VPD_DATA, 0);
AT_WRITE_REG(hw, REG_VPD_CAP, control);
AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
AT_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
AT_WRITE_REG(hw, 0x1008, value);
AT_WRITE_REG(hw, REG_MASTER_CTRL,
AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data);
AT_WRITE_REG(hw, REG_IDT_TABLE, hw->indirect_tab);
AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, hw->base_cpu);
AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
AT_WRITE_REG(hw, REG_MAC_CTRL, value);
AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
AT_WRITE_REG(hw, REG_ISR, ~0);
AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
AT_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_LED_MODE |
AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
AT_WRITE_REG(hw, REG_SMB_STAT_TIMER, hw->smb_timer);
AT_WRITE_REG(hw, REG_ISR, 0x7fffffff);
AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
AT_WRITE_REG(hw, REG_IMR,
AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
AT_WRITE_REG(&adapter->hw, REG_DEBUG_DATA0,
AT_WRITE_REG(&adapter->hw, REG_IMR, imr_data | ISR_RX_EVENT);
AT_WRITE_REG(hw, REG_MAC_CTRL, value);
AT_WRITE_REG(&adapter->hw, REG_MB_TPD_PROD_IDX, tx_ring->next_to_use);
AT_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
AT_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
AT_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
AT_WRITE_REG(hw, REG_TPD_BASE_ADDR_LO,
AT_WRITE_REG(hw, REG_TPD_RING_SIZE, (u16)(tx_ring->count));
AT_WRITE_REG(hw, REG_HOST_TX_CMB_LO,
AT_WRITE_REG(hw, atl1e_rx_page_hi_addr_regs[i],
AT_WRITE_REG(hw, atl1e_rx_page_lo_addr_regs[i][j],
AT_WRITE_REG(hw, atl1e_rx_page_write_offset_regs[i][j],
AT_WRITE_REG(hw, REG_HOST_RXFPAGE_SIZE, rx_ring->page_size);
AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
AT_WRITE_REG(hw, REG_TX_EARLY_TH, (jumbo_thresh + 7) >> 3);
AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
AT_WRITE_REG(hw, REG_RXQ_RXF_PAUSE_THRESH, rxf_thresh_data);