PCI_CFG_SPACE_SIZE
if (!pci_request_config_region_exclusive(root, 0, PCI_CFG_SPACE_SIZE, NULL)) {
int pos = PCI_CFG_SPACE_SIZE, prev = 0;
if (cap_pos == PCI_CFG_SPACE_SIZE) {
if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
} else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) {
reg -= PCI_CFG_SPACE_SIZE;
} else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) {
reg -= PCI_CFG_SPACE_SIZE;
if (pdev->cfg_size > PCI_CFG_SPACE_SIZE)
return PCI_CFG_SPACE_SIZE;
if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
u16 __pos = (start) ?: PCI_CFG_SPACE_SIZE; \
__ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; \
while (__ttl-- > 0 && __pos >= PCI_CFG_SPACE_SIZE) { \
for (pos = PCI_CFG_SPACE_SIZE;
pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
int pos = PCI_CFG_SPACE_SIZE;
return PCI_CFG_SPACE_SIZE;
return PCI_CFG_SPACE_SIZE;
return PCI_CFG_SPACE_SIZE;
return PCI_CFG_SPACE_SIZE;
return PCI_CFG_SPACE_SIZE;
u32 value[PCI_CFG_SPACE_SIZE / sizeof(u32)];
ret = pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status);
pdev->cfg_size = PCI_CFG_SPACE_SIZE;
int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE :
if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE,
if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword);
loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF;
epos = PCI_CFG_SPACE_SIZE;
loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF;
while (loops-- && epos >= PCI_CFG_SPACE_SIZE) {
*(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0;
if (*ppos >= PCI_CFG_SPACE_SIZE) {
if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */