AT_READ_REG
AT_READ_REG(hw, REG_PM_CTRL, p++);
AT_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL, p++);
AT_READ_REG(hw, REG_TWSI_CTRL, p++);
AT_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL, p++);
AT_READ_REG(hw, REG_MASTER_CTRL, p++);
AT_READ_REG(hw, REG_MANUAL_TIMER_INIT, p++);
AT_READ_REG(hw, REG_IRQ_MODRT_TIMER_INIT, p++);
AT_READ_REG(hw, REG_GPHY_CTRL, p++);
AT_READ_REG(hw, REG_LINK_CTRL, p++);
AT_READ_REG(hw, REG_IDLE_STATUS, p++);
AT_READ_REG(hw, REG_MDIO_CTRL, p++);
AT_READ_REG(hw, REG_SERDES, p++);
AT_READ_REG(hw, REG_MAC_CTRL, p++);
AT_READ_REG(hw, REG_MAC_IPG_IFG, p++);
AT_READ_REG(hw, REG_MAC_STA_ADDR, p++);
AT_READ_REG(hw, REG_MAC_STA_ADDR+4, p++);
AT_READ_REG(hw, REG_RX_HASH_TABLE, p++);
AT_READ_REG(hw, REG_RX_HASH_TABLE+4, p++);
AT_READ_REG(hw, REG_RXQ_CTRL, p++);
AT_READ_REG(hw, REG_TXQ_CTRL, p++);
AT_READ_REG(hw, REG_MTU, p++);
AT_READ_REG(hw, REG_WOL_CTRL, p++);
AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
AT_READ_REG(hw, REG_EEPROM_CTRL, &control);
AT_READ_REG(hw, REG_EEPROM_CTRL, &data);
AT_READ_REG(hw, REG_EEPROM_DATA_LO, p_value);
AT_READ_REG(hw, REG_TWSI_DEBUG, &data);
AT_READ_REG(hw, REG_MDIO_CTRL, &val);
AT_READ_REG(hw, REG_MASTER_CTRL, &data);
AT_READ_REG(hw, REG_MDIO_CTRL, &val);
AT_READ_REG(hw, REG_GPHY_CTRL, &phy_ctrl_data);
AT_READ_REG(hw, REG_LPI_CTRL, &lpi_ctrl);
AT_READ_REG(hw, REG_MAC_STA_ADDR, &addr[0]);
AT_READ_REG(hw, REG_MAC_STA_ADDR + 4, &addr[1]);
AT_READ_REG(hw, REG_MT_SPEED, &spd);
AT_READ_REG(hw, REG_MT_SPEED, &spd);
AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl);
AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl);
AT_READ_REG(hw, REG_GPHY_CTRL, &phy_ctrl);
AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
AT_READ_REG(hw, REG_PCIE_PHYMISC2, &data);
AT_READ_REG(hw, REG_LINK_CTRL, &data);
AT_READ_REG(hw, REG_RXQ_CTRL, &data);
AT_READ_REG(hw, REG_TXQ_CTRL, &data);
AT_READ_REG(hw, REG_MAC_CTRL, &data);
AT_READ_REG(hw, REG_PM_CTRL, &data);
AT_READ_REG(hw, REG_TXQ_CTRL, &txq);
AT_READ_REG(hw, REG_RXQ_CTRL, &rxq);
AT_READ_REG(hw, REG_MAC_CTRL, &mac);
AT_READ_REG(hw, REG_DMA_DBG, &data);
AT_READ_REG(hw, REG_MASTER_CTRL, &ctrl_data);
AT_READ_REG(hw, REG_MAC_CTRL, &ctrl_data);
AT_READ_REG(hw, REG_SERDES, &ctrl_data);
AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
AT_READ_REG(&adapter->hw, REG_MT_MODE, &mode);
AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
AT_READ_REG(hw, REG_WOL_CTRL, &data);
AT_READ_REG(hw, REG_ISR, ®_data);
AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &data);
AT_READ_REG(hw, REG_IDLE_STATUS, &data);
AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
AT_READ_REG(&adapter->hw, REG_MAC_CTRL, &mac_ctrl_data);
AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
AT_READ_REG(hw, REG_MASTER_CTRL, &mst_data);
AT_READ_REG(hw, REG_PCIE_PHYMISC, &data);
regs_buff[0] = AT_READ_REG(hw, REG_VPD_CAP);
regs_buff[1] = AT_READ_REG(hw, REG_SPI_FLASH_CTRL);
regs_buff[2] = AT_READ_REG(hw, REG_SPI_FLASH_CONFIG);
regs_buff[3] = AT_READ_REG(hw, REG_TWSI_CTRL);
regs_buff[4] = AT_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
regs_buff[5] = AT_READ_REG(hw, REG_MASTER_CTRL);
regs_buff[6] = AT_READ_REG(hw, REG_MANUAL_TIMER_INIT);
regs_buff[7] = AT_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
regs_buff[8] = AT_READ_REG(hw, REG_GPHY_CTRL);
regs_buff[9] = AT_READ_REG(hw, REG_CMBDISDMA_TIMER);
regs_buff[10] = AT_READ_REG(hw, REG_IDLE_STATUS);
regs_buff[11] = AT_READ_REG(hw, REG_MDIO_CTRL);
regs_buff[12] = AT_READ_REG(hw, REG_SERDES_LOCK);
regs_buff[13] = AT_READ_REG(hw, REG_MAC_CTRL);
regs_buff[14] = AT_READ_REG(hw, REG_MAC_IPG_IFG);
regs_buff[15] = AT_READ_REG(hw, REG_MAC_STA_ADDR);
regs_buff[16] = AT_READ_REG(hw, REG_MAC_STA_ADDR+4);
regs_buff[17] = AT_READ_REG(hw, REG_RX_HASH_TABLE);
regs_buff[18] = AT_READ_REG(hw, REG_RX_HASH_TABLE+4);
regs_buff[19] = AT_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
regs_buff[20] = AT_READ_REG(hw, REG_MTU);
regs_buff[21] = AT_READ_REG(hw, REG_WOL_CTRL);
regs_buff[22] = AT_READ_REG(hw, REG_SRAM_TRD_ADDR);
regs_buff[23] = AT_READ_REG(hw, REG_SRAM_TRD_LEN);
regs_buff[24] = AT_READ_REG(hw, REG_SRAM_RXF_ADDR);
regs_buff[25] = AT_READ_REG(hw, REG_SRAM_RXF_LEN);
regs_buff[26] = AT_READ_REG(hw, REG_SRAM_TXF_ADDR);
regs_buff[27] = AT_READ_REG(hw, REG_SRAM_TXF_LEN);
regs_buff[28] = AT_READ_REG(hw, REG_SRAM_TCPH_ADDR);
regs_buff[29] = AT_READ_REG(hw, REG_SRAM_PKTH_ADDR);
control = AT_READ_REG(hw, REG_VPD_CAP);
*p_value = AT_READ_REG(hw, REG_VPD_DATA);
val = AT_READ_REG(hw, REG_MDIO_CTRL);
value = AT_READ_REG(hw, REG_SPI_FLASH_CTRL);
val = AT_READ_REG(hw, REG_MDIO_CTRL);
value = AT_READ_REG(hw, 0x1008);
val = AT_READ_REG(hw, REG_MDIO_CTRL);
idle_status_data = AT_READ_REG(hw, REG_IDLE_STATUS);
twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
addr[0] = AT_READ_REG(hw, REG_MAC_STA_ADDR);
addr[1] = AT_READ_REG(hw, REG_MAC_STA_ADDR + 4);
intr_status_data = AT_READ_REG(hw, REG_ISR);
*stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
*stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
status = AT_READ_REG(hw, REG_ISR);
imr_data = AT_READ_REG(&adapter->hw, REG_IMR);
value = AT_READ_REG(hw, REG_MAC_CTRL);
val = AT_READ_REG(&adapter->hw, REG_MASTER_CTRL);
ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
AT_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
mac_ctrl_data = AT_READ_REG(hw, REG_MAC_CTRL);
mac_ctrl_data = AT_READ_REG(&adapter->hw, REG_MAC_CTRL);
mac_ctrl_data = AT_READ_REG(&adapter->hw, REG_MAC_CTRL);
phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
dev_ctrl_data = AT_READ_REG(hw, REG_DEVICE_CTRL);
rxf_len = AT_READ_REG(hw, REG_SRAM_RXF_LEN);