PCIE
case PCIE:
case PCIE:
[PCIE] = "PCIE",
def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL);
WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL, data);
def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7);
WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7, data);
def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3);
WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3, data);
def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4);
WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4, data);
def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL);
WREG32_SOC15(PCIE, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL, data);
def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL);
WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL, data);
def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3);
WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3, data);
#define PCIE_CFG_REG_PL2 (PCIE + 0x000000000708)
#define PCIE_CFG_REG_PL3 (PCIE + 0x00000000070C)
#define PCIE_CFG_REG_PL102 (PCIE + 0x000000000898)
#define PCIE_CFG_REG_PL103 (PCIE + 0x00000000089C)
#define PCIE_CFG_REG_PL105 (PCIE + 0x0000000008A4)
#define PCIE_CFG_REG_PL100 (PCIE + 0x000000000890)
#define PCIE_CFG_REG_PL101 (PCIE + 0x000000000894)
#define PCIE_CFG_REG_PL106 (PCIE + 0x0000000008A8)
#define PCI_CFG_MSIX0 (PCIE + 0x0000000000B0)
#define PCI_CFG_REG1 (PCIE + 0x000000000004)
#define PCI_CFG_REG11 (PCIE + 0x00000000002C)
#define PCIE_CFG_SPCIE1 (PCIE + 0x00000000014C)
#define PCIE_CFG_SPCIE2 (PCIE + 0x000000000150)
#define PCIE_CFG_TPH2 (PCIE + 0x000000000180)
brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
brcmf_dbg(PCIE, "RING !\n");
brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
brcmf_dbg(PCIE, "Using TCM indices\n");
brcmf_dbg(PCIE, "Using host memory indices\n");
brcmf_dbg(PCIE, "Nr of flowrings is %d\n", max_flowrings);
brcmf_dbg(PCIE, "Enter\n");
brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len);
brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n",
brcmf_dbg(PCIE, "PCIe protocol version %d\n", shared->version);
brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
brcmf_dbg(PCIE, "Halt ARM.\n");
brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
brcmf_dbg(PCIE, "Download random seed\n");
brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
brcmf_dbg(PCIE, "Bring ARM in running state\n");
brcmf_dbg(PCIE, "Wait for FW init\n");
brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n",
brcmf_dbg(PCIE, "OTP: chip_params='%s' board_params='%s'\n",
brcmf_dbg(PCIE, "OTP: module=%s vendor=%s version=%s\n",
brcmf_dbg(PCIE, "parse_otp size=%zd\n", size);
brcmf_dbg(PCIE, "OTP @ 0x%x (%d): SYS_VENDOR\n",
brcmf_dbg(PCIE, "OTP @ 0x%x (%d): BRCM_CIS\n",
brcmf_dbg(PCIE, "OTP @ 0x%x (%d): Unknown type 0x%x\n",
brcmf_dbg(PCIE, "OTP data:\n");
brcmf_dbg(PCIE, "[%8x] 0x%04x\n", base + 2 * idx, otp[idx]);
brcmf_dbg(PCIE, "Apple board: %s\n",
brcmf_dbg(PCIE, "Board: %s\n", devinfo->settings->board_type);
brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device);
brcmf_dbg(PCIE, "Enter\n");
brcmf_dbg(PCIE, "Enter\n");
brcmf_dbg(PCIE, "Enter\n");
brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus);
brcmf_dbg(PCIE, "Try to wakeup device....\n");
brcmf_dbg(PCIE, "Hot resume, continue....\n");
brcmf_dbg(PCIE, "Enter\n");
brcmf_dbg(PCIE, "Enter\n");
brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
brcmf_dbg(PCIE, "D2H_MB_DATA: FW HALT\n");
brcmf_dbg(PCIE, "Enter\n");
brcmf_dbg(PCIE, "Enter %x\n", status);
brcmf_dbg(PCIE, "Enter\n");
if (priv->mode == PCIE)
if (priv->mode == PCIE)
if (priv->mode != SATA && priv->mode != PCIE) {
else if (priv->mode == PCIE)
else if (priv->mode == PCIE)
if (priv->mode != SATA && priv->mode != PCIE) {
PCIE##x##_CFG_AUX_CLK_EN | \
PCIE##x##_CFG_CORE_CLK_EN | \
PCIE##x##_CFG_POWERUP_RESET | \
PCIE##x##_CFG_DEVICE_PRESENT)
MUX_PG(gpv, PCIE, RSVD2, RSVD3, RSVD4, 0x14, 17, 0x8c, 2, 0xa0, 30),
MUX_PG(slxa, PCIE, SPI4, SDIO3, SPI2, 0x18, 3, 0x84, 6, 0xa4, 22),
MUX_PG(slxk, PCIE, SPI4, SDIO3, SPI2, 0x18, 7, 0x84, 14, 0xa4, 30),
PINGROUP(pex_l2_rst_n_pcc6, PCIE, HDA, RSVD3, RSVD4, 0x33d8, N, N),
PINGROUP(pex_l2_clkreq_n_pcc7, PCIE, HDA, RSVD3, RSVD4, 0x33dc, N, N),
PINGROUP(pex_l0_prsnt_n_pdd0, PCIE, HDA, RSVD3, RSVD4, 0x33b8, N, N),
PINGROUP(pex_l0_rst_n_pdd1, PCIE, HDA, RSVD3, RSVD4, 0x33bc, N, N),
PINGROUP(pex_l0_clkreq_n_pdd2, PCIE, HDA, RSVD3, RSVD4, 0x33c0, N, N),
PINGROUP(pex_wake_n_pdd3, PCIE, HDA, RSVD3, RSVD4, 0x33c4, N, N),
PINGROUP(pex_l1_prsnt_n_pdd4, PCIE, HDA, RSVD3, RSVD4, 0x33c8, N, N),
PINGROUP(pex_l1_rst_n_pdd5, PCIE, HDA, RSVD3, RSVD4, 0x33cc, N, N),
PINGROUP(pex_l1_clkreq_n_pdd6, PCIE, HDA, RSVD3, RSVD4, 0x33d0, N, N),
PINGROUP(pex_l2_prsnt_n_pdd7, PCIE, HDA, RSVD3, RSVD4, 0x33d4, N, N),
u8 PCIE:1;