PAGE0
free_mem_end_ptr = PAGE0->imm_max_mem;
(unsigned long)(PAGE0->mem_pdc_hi) << 32 |
(unsigned long)PAGE0->mem_pdc);
# define MEM_PDC (unsigned long)(PAGE0->mem_pdc_hi) << 32 | PAGE0->mem_pdc
# define MEM_PDC (unsigned long)PAGE0->mem_pdc
real32_call(PAGE0->mem_cons.iodc_io,
(unsigned long)PAGE0->mem_cons.hpa, ENTRY_IO_COUT,
PAGE0->mem_cons.spa, __pa(PAGE0->mem_cons.dp.layers),
if (!PAGE0->mem_kbd.iodc_io)
real32_call(PAGE0->mem_kbd.iodc_io,
(unsigned long)PAGE0->mem_kbd.hpa, ENTRY_IO_CIN,
PAGE0->mem_kbd.spa, __pa(PAGE0->mem_kbd.dp.layers),
npages = (PAGE_ALIGN(PAGE0->imm_max_mem) >> PAGE_SHIFT);
base = ((unsigned long long) PAGE0->pad0[2] << 32)
| PAGE0->pad0[3]; /* SeaBIOS stored it here */
*(unsigned long *)(virt + kexec_free_mem_offset) = PAGE0->mem_free;
kbuf.buf_min = PAGE0->mem_free + PAGE_SIZE;
if (PAGE0->mem_cons.cl_class == CL_DUPLEX)
memcpy(&PAGE0->mem_kbd, &PAGE0->mem_cons, sizeof(PAGE0->mem_cons));
boot_cpu_data.cpu_hz = 100 * PAGE0->mem_10msec; /* Hz of this PARISC */
running_on_qemu = (memcmp(&PAGE0->pad0, "SeaBIOS", 8) == 0);
if (PAGE0->mem_cons.cl_class == CL_DUPLEX)
WARN_ON(((unsigned long)(PAGE0->mem_pdc_hi) << 32
| PAGE0->mem_pdc) != pdce_proc);
cr16_clock_freq = 100 * PAGE0->mem_10msec; /* Hz */
PAGE0->vec_toc = __pa(toc_code) & 0xffffffff;
PAGE0->vec_toc_hi = __pa(toc_code) >> 32;
PAGE0->vec_toclen = toc_handler_size;
memblock_reserve(0UL, (unsigned long)(PAGE0->mem_free +
if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
&& (PAGE0->mem_boot.cl_class != CL_SEQU)) {
PAGE0->mem_cons.cl_class != CL_DUPLEX);
sti = sti_try_rom_generic(PAGE0->proc_sti, hpa, NULL);