drivers/gpu/drm/i915/display/intel_dp_aux.c

632

return PCH_DP_AUX_CH_CTL(aux_ch);

drivers/gpu/drm/i915/gvt/handlers.c

1105

else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_B)) ||

drivers/gpu/drm/i915/gvt/handlers.c

1108

else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_C)) ||

drivers/gpu/drm/i915/gvt/handlers.c

1111

else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_D)) ||

drivers/gpu/drm/i915/gvt/handlers.c

1211

PCH_DP_AUX_CH_CTL(port_index) :

drivers/gpu/drm/i915/gvt/handlers.c

2331

MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2333

MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2335

MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

901

MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

902

MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

903

MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4);