drivers/char/hw_random/via-rng.c

89

char buf[16 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__

drivers/char/hw_random/via-rng.c

91

u32 *via_rng_datum = (u32 *)PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);

drivers/crypto/padlock-aes.c

218

u8 buf[AES_BLOCK_SIZE * (MAX_ECB_FETCH_BLOCKS - 1) + PADLOCK_ALIGNMENT - 1];

drivers/crypto/padlock-aes.c

219

u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);

drivers/crypto/padlock-aes.c

232

u8 buf[AES_BLOCK_SIZE * (MAX_CBC_FETCH_BLOCKS - 1) + PADLOCK_ALIGNMENT - 1];

drivers/crypto/padlock-aes.c

233

u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);

drivers/crypto/padlock-aes.c

331

.cra_alignmask = PADLOCK_ALIGNMENT - 1,

drivers/crypto/padlock-aes.c

400

.base.cra_alignmask = PADLOCK_ALIGNMENT - 1,

drivers/crypto/padlock-aes.c

467

.base.cra_alignmask = PADLOCK_ALIGNMENT - 1,

drivers/crypto/padlock-aes.c

51

} __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));

drivers/crypto/padlock-aes.c

62

__attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));

drivers/crypto/padlock-aes.c

64

__attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));

drivers/crypto/padlock-aes.c

90

unsigned long align = PADLOCK_ALIGNMENT;

drivers/crypto/padlock-sha.c

20

#define PADLOCK_SHA_DESCSIZE (128 + ((PADLOCK_ALIGNMENT - 1) & \

drivers/crypto/padlock-sha.c

29

return PTR_ALIGN(shash_desc_ctx(desc), PADLOCK_ALIGNMENT);