PA_FPGA
#define FPGA_SRSTR (PA_FPGA + 0x000) /* System reset */
#define FPGA_IRQ0SR (PA_FPGA + 0x010) /* IRQ0 status */
#define FPGA_IRQ0MR (PA_FPGA + 0x020) /* IRQ0 mask */
#define FPGA_BDMR (PA_FPGA + 0x030) /* Board operating mode */
#define FPGA_INTT0PRTR (PA_FPGA + 0x040) /* Interrupt test mode0 port */
#define FPGA_INTT0SELR (PA_FPGA + 0x050) /* Int. test mode0 select */
#define FPGA_INTT1POLR (PA_FPGA + 0x060) /* Int. test mode0 polarity */
#define FPGA_NMIR (PA_FPGA + 0x070) /* NMI source */
#define FPGA_NMIMR (PA_FPGA + 0x080) /* NMI mask */
#define FPGA_IRQR (PA_FPGA + 0x090) /* IRQX source */
#define FPGA_IRQMR (PA_FPGA + 0x0A0) /* IRQX mask */
#define FPGA_SLEDR (PA_FPGA + 0x0B0) /* LED control */
#define FPGA_MAPSWR (PA_FPGA + 0x0C0) /* Map switch */
#define FPGA_FPVERR (PA_FPGA + 0x0D0) /* FPGA version */
#define FPGA_FPDATER (PA_FPGA + 0x0E0) /* FPGA date */
#define FPGA_RSE (PA_FPGA + 0x100) /* Reset source */
#define FPGA_EASR (PA_FPGA + 0x110) /* External area select */
#define FPGA_SPER (PA_FPGA + 0x120) /* Serial port enable */
#define FPGA_IMSR (PA_FPGA + 0x130) /* Interrupt mode select */
#define FPGA_PCIMR (PA_FPGA + 0x140) /* PCI Mode */
#define FPGA_DIPSWMR (PA_FPGA + 0x150) /* DIPSW monitor */
#define FPGA_FPODR (PA_FPGA + 0x160) /* Output port data */
#define FPGA_ATAESR (PA_FPGA + 0x170) /* ATA extended bus status */
#define FPGA_IRQPOLR (PA_FPGA + 0x180) /* IRQx polarity */
#define FPGA_ILSR1 (PA_FPGA + 0x02)
#define FPGA_ILSR2 (PA_FPGA + 0x03)
#define FPGA_ILSR3 (PA_FPGA + 0x04)
#define FPGA_ILSR4 (PA_FPGA + 0x05)
#define FPGA_ILSR5 (PA_FPGA + 0x06)
#define FPGA_ILSR6 (PA_FPGA + 0x07)
#define FPGA_ILSR7 (PA_FPGA + 0x08)
#define FPGA_ILSR8 (PA_FPGA + 0x09)
#define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */
#define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */
#define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */
#define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */
#define FPGA_INTSEL2 (PA_FPGA + 8) /* Interrupt select register 2 */
#define FPGA_INTSEL3 (PA_FPGA + 10) /* Interrupt select register 3 */
#define FPGA_PCI_INTSEL1 (PA_FPGA + 12) /* PCI Interrupt select register 1 */
#define FPGA_PCI_INTSEL2 (PA_FPGA + 14) /* PCI Interrupt select register 2 */
#define FPGA_INTSET (PA_FPGA + 16) /* IRQ/IRL select register */
#define FPGA_INTSTS1 (PA_FPGA + 18) /* Interrupt status register 1 */
#define FPGA_INTSTS2 (PA_FPGA + 20) /* Interrupt status register 2 */
#define FPGA_REQSEL (PA_FPGA + 22) /* REQ/GNT select register */
#define FPGA_DBG_LED (PA_FPGA + 32) /* Debug LED(D-LED[8:1] */
#define FPGA_IVDRID (PA_FPGA + 36) /* iVDR ID Register */
#define FPGA_IVDRPW (PA_FPGA + 38) /* iVDR Power ON Register */
#define FPGA_MMCID (PA_FPGA + 40) /* MMC ID Register */