drivers/gpu/drm/nouveau/dispnv50/base907c.c

166

NVDEF(NV907C, SET_CSC_RED2RED, OWNER, CORE));

drivers/gpu/drm/nouveau/dispnv50/base907c.c

180

NVDEF(NV907C, SET_CSC_RED2RED, OWNER, BASE) |

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

45

NVDEF(NVC37D, WINDOW_SET_CONTROL, OWNER, HEAD(i >> 1)));

drivers/gpu/drm/nouveau/dispnv50/disp.c

1548

if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE))

drivers/gpu/drm/nouveau/dispnv50/disp.c

1974

const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE);

drivers/gpu/drm/nouveau/dispnv50/disp.c

1991

case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break;

drivers/gpu/drm/nouveau/dispnv50/disp.c

1992

case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break;

drivers/gpu/drm/nouveau/dispnv50/disp.c

486

const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE);

drivers/gpu/drm/nouveau/dispnv50/disp.c

503

case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break;

drivers/gpu/drm/nouveau/dispnv50/disp.c

504

case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break;

drivers/gpu/drm/tegra/hub.c

290

value |= OWNER(new->pipe);

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

538

SQ_CTXT_WQ_PAGE_SET(1, OWNER));

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

564

SQ_CTXT_PREF_SET(1, OWNER));

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

620

RQ_CTXT_WQ_PAGE_SET(1, OWNER));

drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.c

637

RQ_CTXT_PREF_SET(1, OWNER));

drivers/net/ethernet/huawei/hinic3/hinic3_tx.c

496

SQ_CTRL_SET(owner, OWNER));

drivers/net/ethernet/huawei/hinic3/hinic3_tx.c

508

SQ_CTRL_SET(owner, OWNER));