OWL_DIVIDER_HW
.div_hw = OWL_DIVIDER_HW(_reg, _shift, _width, \
OWL_DIVIDER_HW(CMU_BUSCLK1, 16, 2, 0, NULL),
OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL),
OWL_DIVIDER_HW(CMU_BISPCLK, 0, 4, 0, std12rate_div_table),
OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, std12rate_div_table),
OWL_DIVIDER_HW(CMU_SENSORCLK, 8, 4, 0, std12rate_div_table),
OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, i2s_div_table),
OWL_DIVIDER_HW(CMU_AUDIOPLL, 28, 4, 0, i2s_div_table),
OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, nand_div_table),
OWL_DIVIDER_HW(CMU_NANDCCLK, 4, 3, 0, nand_div_table),
OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
OWL_DIVIDER_HW(CMU_SICLK, 0, 4, 0, NULL),
OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, NULL),
OWL_DIVIDER_HW(CMU_UART0CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART1CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART2CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART3CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART4CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART5CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART6CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, hdmia_div_table),
OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, hdmia_div_table),
OWL_DIVIDER_HW(CMU_SENSORCLK, 5, 2, 0, NULL),
OWL_DIVIDER_HW(CMU_SSTSCLK, 20, 10, 0, NULL),
OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
OWL_DIVIDER_HW(CMU_CSICLK, 16, 4, 0, NULL),
OWL_DIVIDER_HW(CMU_ASSISTPLL, 10, 1, 0, eth_mac_div_table),
OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
OWL_DIVIDER_HW(CMU_LCDCLK, 0, 5, 0, NULL),
OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 4, 0, nand_div_table),
OWL_DIVIDER_HW(CMU_NANDCCLK, 16, 4, 0, nand_div_table),
OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 6, 0, NULL),
OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 6, 0, NULL),
OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 6, 0, NULL),
OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 6, 0, NULL),
OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 6, 0, NULL),
OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 6, 0, NULL),
OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, NULL),
OWL_DIVIDER_HW(CMU_TLSCLK, 0, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
OWL_DIVIDER_HW(CMU_TLSCLK, 8, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART1CLK, 1, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),