PACKET3_SET_UCONFIG_REG_START
PACKET3_SET_UCONFIG_REG_START);
PACKET3_SET_UCONFIG_REG_START);
PACKET3_SET_UCONFIG_REG_START);
PACKET3_SET_UCONFIG_REG_START);
amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START);
ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START;
amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START);
amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START);
(SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START);
radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2));
PACKET3_SET_UCONFIG_REG_START) >> 2));
ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2);