drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

2432

buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

4338

ctx_reg_offset = SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6400

PACKET3_SET_CONTEXT_REG_START);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6408

SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3651

PACKET3_SET_CONTEXT_REG_START);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3659

SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

871

ctx_reg_offset = SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2046

amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2871

buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2491

amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2499

amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3891

buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

1236

buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4165

ext->reg_index - PACKET3_SET_CONTEXT_REG_START);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4173

amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3363

ext->reg_index - PACKET3_SET_CONTEXT_REG_START);

drivers/gpu/drm/radeon/cik.c

6732

buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);

drivers/gpu/drm/radeon/evergreen_cs.c

2319

start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;

drivers/gpu/drm/radeon/evergreen_cs.c

2321

if ((start_reg < PACKET3_SET_CONTEXT_REG_START) ||

drivers/gpu/drm/radeon/evergreen_cs.c

2631

allowed_reg_base -= PACKET3_SET_CONTEXT_REG_START;

drivers/gpu/drm/radeon/evergreen_cs.c

3600

allowed_reg_base -= PACKET3_SET_CONTEXT_REG_START;

drivers/gpu/drm/radeon/si.c

5728

buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);