PACKET3_SET_CONTEXT_REG
buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
PACKET3(PACKET3_SET_CONTEXT_REG,
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
PACKET3(PACKET3_SET_CONTEXT_REG,
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
PACKET3(PACKET3_SET_CONTEXT_REG,
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
PACKET3(PACKET3_SET_CONTEXT_REG,
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
case PACKET3_SET_CONTEXT_REG:
case PACKET3_SET_CONTEXT_REG:
case PACKET3_SET_CONTEXT_REG:
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
case PACKET3_SET_CONTEXT_REG:
case PACKET3_SET_CONTEXT_REG:
cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));