PACKET3_SET_CONFIG_REG_START
amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START);
amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START;
amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
PACKET3_SET_CONFIG_REG_START) >> 2));
start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
PACKET3_SET_CONFIG_REG_START) >> 2));
radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
PACKET3_SET_CONFIG_REG_START) >> 2));
radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||