PACKET3_SET_BASE
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
case PACKET3_SET_BASE:
case PACKET3_SET_BASE:
radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
case PACKET3_SET_BASE:
case PACKET3_SET_BASE:
case PACKET3_SET_BASE: