P54U_WRITE
P54U_WRITE(NET2280_BRG_U32, NET2280_GPIOCTL, reg);
P54U_WRITE(NET2280_BRG_U32, NET2280_GPIOCTL, reg);
P54U_WRITE(NET2280_BRG_U32, NET2280_DEVINIT,
P54U_WRITE(NET2280_BRG_CFG_U16, PCI_COMMAND,
P54U_WRITE(NET2280_BRG_CFG_U32, PCI_BASE_ADDRESS_0,
P54U_WRITE(NET2280_BRG_CFG_U16, PCI_STATUS, reg);
P54U_WRITE(NET2280_BRG_U32, NET2280_EPA_RSP,
P54U_WRITE(NET2280_BRG_U32, NET2280_EPC_RSP,
P54U_WRITE(NET2280_BRG_CFG_U32, PCI_BASE_ADDRESS_2,
P54U_WRITE(NET2280_DEV_CFG_U16, 0x10000 | PCI_COMMAND,
P54U_WRITE(NET2280_DEV_CFG_U16, 0x10000 | 0x40 /* TRDY timeout */, 0);
P54U_WRITE(NET2280_DEV_CFG_U32, 0x10000 | PCI_BASE_ADDRESS_0,
P54U_WRITE(NET2280_BRG_U32, NET2280_USBIRQENB1, 0);
P54U_WRITE(NET2280_BRG_U32, NET2280_IRQSTAT1,
P54U_WRITE(NET2280_DEV_U32, &devreg->int_enable, 0);
P54U_WRITE(NET2280_DEV_U32, &devreg->ctrl_stat, reg);
P54U_WRITE(NET2280_DEV_U32, &devreg->ctrl_stat, reg);
P54U_WRITE(NET2280_DEV_U32, &devreg->ctrl_stat, reg);
P54U_WRITE(NET2280_DEV_U32, &devreg->int_ack, reg);
P54U_WRITE(NET2280_DEV_U32, &devreg->direct_mem_base,
P54U_WRITE(NET2280_DEV_U32,
P54U_WRITE(NET2280_DEV_U32,
P54U_WRITE(NET2280_DEV_U32,
P54U_WRITE(NET2280_DEV_U32,
P54U_WRITE(NET2280_DEV_U32, &devreg->dma_addr,
P54U_WRITE(NET2280_DEV_U32, &devreg->dma_len,
P54U_WRITE(NET2280_DEV_U32, &devreg->dma_ctrl,
P54U_WRITE(NET2280_BRG_U32, NET2280_EPA_STAT,
P54U_WRITE(NET2280_DEV_U32, &devreg->ctrl_stat, reg);
P54U_WRITE(NET2280_DEV_U32, &devreg->ctrl_stat, reg);
P54U_WRITE(NET2280_DEV_U32, &devreg->ctrl_stat, reg);
P54U_WRITE(NET2280_DEV_U32, &devreg->int_ack, reg);
P54U_WRITE(NET2280_DEV_U32, &devreg->int_enable,
P54U_WRITE(NET2280_BRG_U32, NET2280_IRQSTAT1,
P54U_WRITE(NET2280_BRG_U32, NET2280_USBIRQENB1,
P54U_WRITE(NET2280_DEV_U32, &devreg->dev_int,
P54U_WRITE(NET2280_DEV_U32, &devreg->int_ack, reg);
P54U_WRITE(NET2280_BRG_U32, NET2280_USBIRQENB1, 0);
P54U_WRITE(NET2280_BRG_U32, NET2280_IRQSTAT1,