arch/x86/events/intel/p4.c

185

[P4_EVENT_IOQ_ACTIVE_ENTRIES] = { /* shared ESCR */

arch/x86/events/intel/p4.c

186

.opcode = P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES),

arch/x86/events/intel/p4.c

189

P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT) |

arch/x86/events/intel/p4.c

190

P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ) |

arch/x86/events/intel/p4.c

191

P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE) |

arch/x86/events/intel/p4.c

192

P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC) |

arch/x86/events/intel/p4.c

193

P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC) |

arch/x86/events/intel/p4.c

194

P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT) |

arch/x86/events/intel/p4.c

195

P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP) |

arch/x86/events/intel/p4.c

196

P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB) |

arch/x86/events/intel/p4.c

197

P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN) |

arch/x86/events/intel/p4.c

198

P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER) |

arch/x86/events/intel/p4.c

199

P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH),