arch/x86/events/intel/p4.c

153

[P4_EVENT_BSQ_CACHE_REFERENCE] = {

arch/x86/events/intel/p4.c

154

.opcode = P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE),

arch/x86/events/intel/p4.c

157

P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS) |

arch/x86/events/intel/p4.c

158

P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE) |

arch/x86/events/intel/p4.c

159

P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM) |

arch/x86/events/intel/p4.c

160

P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS) |

arch/x86/events/intel/p4.c

161

P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE) |

arch/x86/events/intel/p4.c

162

P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM) |

arch/x86/events/intel/p4.c

163

P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS) |

arch/x86/events/intel/p4.c

164

P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS) |

arch/x86/events/intel/p4.c

165

P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS),

arch/x86/events/intel/p4.c

671

p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_BSQ_CACHE_REFERENCE) |

arch/x86/events/intel/p4.c

672

P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS) |

arch/x86/events/intel/p4.c

673

P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE) |

arch/x86/events/intel/p4.c

674

P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM) |

arch/x86/events/intel/p4.c

675

P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS) |

arch/x86/events/intel/p4.c

676

P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE) |

arch/x86/events/intel/p4.c

677

P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM)),

arch/x86/events/intel/p4.c

681

p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_BSQ_CACHE_REFERENCE) |

arch/x86/events/intel/p4.c

682

P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS) |

arch/x86/events/intel/p4.c

683

P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS) |

arch/x86/events/intel/p4.c

684

P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS)),