drivers/net/ethernet/ti/icssm/icssm_prueth.c

154

{ .rd_ptr = P0_Q3_BD_OFFSET, .wr_ptr = P0_Q3_BD_OFFSET, },

drivers/net/ethernet/ti/icssm/icssm_prueth.c

199

writew(P0_Q3_BD_OFFSET, sram + 4);

drivers/net/ethernet/ti/icssm/icssm_prueth.c

78

P0_Q3_BD_OFFSET,

drivers/net/ethernet/ti/icssm/icssm_prueth.c

79

P0_Q3_BD_OFFSET + ((HOST_QUEUE_3_SIZE - 1) * BD_SIZE),

drivers/net/ethernet/ti/icssm/icssm_prueth_switch.c

138

P0_Q3_BD_OFFSET,

drivers/net/ethernet/ti/icssm/icssm_prueth_switch.c

139

P0_Q3_BD_OFFSET + ((HOST_QUEUE_3_SIZE - 1) * BD_SIZE),

drivers/net/ethernet/ti/icssm/icssm_prueth_switch.c

49

P0_Q3_BD_OFFSET,

drivers/net/ethernet/ti/icssm/icssm_prueth_switch.c

50

P0_Q3_BD_OFFSET + ((HOST_QUEUE_3_SIZE - 1) * BD_SIZE),

drivers/net/ethernet/ti/icssm/icssm_prueth_switch.c

866

writew(P0_Q3_BD_OFFSET, dram + 4);

drivers/net/ethernet/ti/icssm/icssm_switch.h

298

#define P0_Q4_BD_OFFSET (P0_Q3_BD_OFFSET + HOST_QUEUE_3_SIZE * BD_SIZE)