drivers/net/ethernet/ti/icssm/icssm_prueth.c

153

{ .rd_ptr = P0_Q2_BD_OFFSET, .wr_ptr = P0_Q2_BD_OFFSET, },

drivers/net/ethernet/ti/icssm/icssm_prueth.c

198

writew(P0_Q2_BD_OFFSET, sram + 2);

drivers/net/ethernet/ti/icssm/icssm_prueth.c

72

P0_Q2_BD_OFFSET,

drivers/net/ethernet/ti/icssm/icssm_prueth.c

73

P0_Q2_BD_OFFSET + ((HOST_QUEUE_2_SIZE - 1) * BD_SIZE),

drivers/net/ethernet/ti/icssm/icssm_prueth_switch.c

132

P0_Q2_BD_OFFSET,

drivers/net/ethernet/ti/icssm/icssm_prueth_switch.c

133

P0_Q2_BD_OFFSET + ((HOST_QUEUE_2_SIZE - 1) * BD_SIZE),

drivers/net/ethernet/ti/icssm/icssm_prueth_switch.c

43

P0_Q2_BD_OFFSET,

drivers/net/ethernet/ti/icssm/icssm_prueth_switch.c

44

P0_Q2_BD_OFFSET + ((HOST_QUEUE_2_SIZE - 1) * BD_SIZE),

drivers/net/ethernet/ti/icssm/icssm_prueth_switch.c

865

writew(P0_Q2_BD_OFFSET, dram + 2);

drivers/net/ethernet/ti/icssm/icssm_switch.h

299

#define P0_Q3_BD_OFFSET (P0_Q2_BD_OFFSET + HOST_QUEUE_2_SIZE * BD_SIZE)