drivers/net/ethernet/ti/icssm/icssm_prueth.c

152

{ .rd_ptr = P0_Q1_BD_OFFSET, .wr_ptr = P0_Q1_BD_OFFSET, },

drivers/net/ethernet/ti/icssm/icssm_prueth.c

197

writew(P0_Q1_BD_OFFSET, sram);

drivers/net/ethernet/ti/icssm/icssm_prueth.c

66

P0_Q1_BD_OFFSET,

drivers/net/ethernet/ti/icssm/icssm_prueth.c

67

P0_Q1_BD_OFFSET + ((HOST_QUEUE_1_SIZE - 1) * BD_SIZE),

drivers/net/ethernet/ti/icssm/icssm_prueth_switch.c

126

P0_Q1_BD_OFFSET,

drivers/net/ethernet/ti/icssm/icssm_prueth_switch.c

127

P0_Q1_BD_OFFSET + ((HOST_QUEUE_1_SIZE - 1) * BD_SIZE),

drivers/net/ethernet/ti/icssm/icssm_prueth_switch.c

37

P0_Q1_BD_OFFSET,

drivers/net/ethernet/ti/icssm/icssm_prueth_switch.c

38

P0_Q1_BD_OFFSET + ((HOST_QUEUE_1_SIZE - 1) * BD_SIZE),

drivers/net/ethernet/ti/icssm/icssm_prueth_switch.c

864

writew(P0_Q1_BD_OFFSET, dram);

drivers/net/ethernet/ti/icssm/icssm_switch.h

300

#define P0_Q2_BD_OFFSET (P0_Q1_BD_OFFSET + HOST_QUEUE_1_SIZE * BD_SIZE)