Op0
encoding = sys_reg(sr->Op0, sr->Op1, sr->CRn, sr->CRm, sr->Op2);
if (!(params.Op0 == 3 && (params.CRn & 0b1011) == 0b1011))
Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
params.Op0 = 0;
params->Op0 = 3;
params->Op0 = 3;
if (params.Op0 == 2 || params.Op0 == 3)
(params.Op0 == 2 || params.Op0 == 3))
params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
(reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
if (p->Op0 == 0) { /* AArch32 */
p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, str_write_read(p->is_write));
sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
if (i1->Op0 != i2->Op0)
return i1->Op0 - i2->Op0;
u8 Op0;
#define Op0(_x) .Op0 = _x
Op0(sys_reg_Op0(reg)), Op1(sys_reg_Op1(reg)), \
Op0(0), Op1(sys_reg_Op1(reg)), \
((struct sys_reg_params){ .Op0 = sys_reg_Op0(reg), \
((struct sys_reg_params){ .Op0 = ((esr) >> 20) & 3, \
return (p->Op0 == 3 && !(p->Op1 & 0b100) && p->Op1 != 2 &&
u8 Op0;
__entry->Op0 = reg->Op0;
__entry->Op0 = reg->Op0;
__entry->Op0, __entry->Op1, __entry->CRn,
__field(u8, Op0)