drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

320

if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) {

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

325

OTG_H_TIMING_DIV_MODE, h_div);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

639

type OTG_H_TIMING_DIV_MODE;\

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

217

OTG_H_TIMING_DIV_MODE, h_div);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

277

REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

326

SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

242

OTG_H_TIMING_DIV_MODE, 0);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

89

REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h

253

SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

102

OTG_H_TIMING_DIV_MODE, opp_cnt - 1);

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

180

OTG_H_TIMING_DIV_MODE, h_div);

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h

250

SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

244

OTG_H_TIMING_DIV_MODE, h_div);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

97

OTG_H_TIMING_DIV_MODE, opp_cnt - 1);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h

178

SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

109

REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

125

OTG_H_TIMING_DIV_MODE, H_TIMING_DIV_BY2);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

144

OTG_H_TIMING_DIV_MODE, H_TIMING_DIV_BY4);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

156

OTG_H_TIMING_DIV_MODE, H_TIMING_DIV_BY4);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

283

OTG_H_TIMING_DIV_MODE, h_div);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h

155

SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\

drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h

192

SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\

drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h

370

SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\