OWL_MUX_HW
.mux_hw = OWL_MUX_HW(_reg, _shift, _width), \
OWL_MUX_HW(CMU_BUSCLK1, 4, 3),
OWL_MUX_HW(CMU_BUSCLK1, 8, 3),
OWL_MUX_HW(CMU_VCECLK, 4, 2),
OWL_MUX_HW(CMU_VDECLK, 4, 2),
OWL_MUX_HW(CMU_BISPCLK, 4, 1),
OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
OWL_MUX_HW(CMU_SD0CLK, 9, 1),
OWL_MUX_HW(CMU_SD1CLK, 9, 1),
OWL_MUX_HW(CMU_SD2CLK, 9, 1),
OWL_MUX_HW(CMU_PWM0CLK, 12, 1),
OWL_MUX_HW(CMU_PWM1CLK, 12, 1),
OWL_MUX_HW(CMU_PWM2CLK, 12, 1),
OWL_MUX_HW(CMU_PWM3CLK, 12, 1),
OWL_MUX_HW(CMU_PWM4CLK, 12, 1),
OWL_MUX_HW(CMU_PWM5CLK, 12, 1),
OWL_MUX_HW(CMU_DECLK, 12, 1),
OWL_MUX_HW(CMU_UART0CLK, 16, 1),
OWL_MUX_HW(CMU_UART1CLK, 16, 1),
OWL_MUX_HW(CMU_UART2CLK, 16, 1),
OWL_MUX_HW(CMU_UART3CLK, 16, 1),
OWL_MUX_HW(CMU_UART4CLK, 16, 1),
OWL_MUX_HW(CMU_UART5CLK, 16, 1),
OWL_MUX_HW(CMU_UART6CLK, 16, 1),
OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
OWL_MUX_HW(CMU_CSICLK, 4, 1),
OWL_MUX_HW(CMU_SICLK, 4, 1),
OWL_MUX_HW(CMU_DECLK, 12, 1),
OWL_MUX_HW(CMU_HDECLK, 4, 2),
OWL_MUX_HW(CMU_VDECLK, 4, 2),
OWL_MUX_HW(CMU_VCECLK, 4, 2),
OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
OWL_MUX_HW(CMU_SD0CLK, 9, 1),
OWL_MUX_HW(CMU_SD1CLK, 9, 1),
OWL_MUX_HW(CMU_SD2CLK, 9, 1),
OWL_MUX_HW(CMU_UART0CLK, 16, 1),
OWL_MUX_HW(CMU_UART1CLK, 16, 1),
OWL_MUX_HW(CMU_UART2CLK, 16, 1),
OWL_MUX_HW(CMU_UART3CLK, 16, 1),
OWL_MUX_HW(CMU_UART4CLK, 16, 1),
OWL_MUX_HW(CMU_UART5CLK, 16, 1),
OWL_MUX_HW(CMU_UART6CLK, 16, 1),
OWL_MUX_HW(CMU_PWM0CLK, 12, 1),
OWL_MUX_HW(CMU_PWM1CLK, 12, 1),
OWL_MUX_HW(CMU_PWM2CLK, 12, 1),
OWL_MUX_HW(CMU_PWM3CLK, 12, 1),
OWL_MUX_HW(CMU_PWM4CLK, 12, 1),
OWL_MUX_HW(CMU_PWM5CLK, 12, 1),
OWL_MUX_HW(CMU_GPU3DCLK, 4, 3),
OWL_MUX_HW(CMU_LCDCLK, 12, 2),
OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), /*CMU_AUDIOPLL 24,1 unused*/
OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
OWL_MUX_HW(CMU_BISPCLK, 4, 1),
OWL_MUX_HW(CMU_CSICLK, 4, 1),
OWL_MUX_HW(CMU_CSICLK, 20, 1),
OWL_MUX_HW(CMU_DECLK, 12, 1),
OWL_MUX_HW(CMU_BUSCLK, 10, 2),
OWL_MUX_HW(CMU_EDPCLK, 19, 1),
OWL_MUX_HW(CMU_GPU3DCLK, 4, 2),
OWL_MUX_HW(CMU_GPU3DCLK, 20, 2),
OWL_MUX_HW(CMU_GPU3DCLK, 28, 2),
OWL_MUX_HW(CMU_HDECLK, 4, 2),
OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
OWL_MUX_HW(CMU_IMXCLK, 4, 1),
OWL_MUX_HW(CMU_LCDCLK, 12, 2),
OWL_MUX_HW(CMU_NANDCCLK, 8, 1),
OWL_MUX_HW(CMU_NANDCCLK, 24, 1),
OWL_MUX_HW(CMU_SD0CLK, 9, 1),
OWL_MUX_HW(CMU_SD1CLK, 9, 1),
OWL_MUX_HW(CMU_SD2CLK, 9, 1),
OWL_MUX_HW(CMU_SD3CLK, 9, 1),
OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
OWL_MUX_HW(CMU_UART0CLK, 16, 1),
OWL_MUX_HW(CMU_UART1CLK, 16, 1),
OWL_MUX_HW(CMU_UART2CLK, 16, 1),
OWL_MUX_HW(CMU_UART3CLK, 16, 1),
OWL_MUX_HW(CMU_UART4CLK, 16, 1),
OWL_MUX_HW(CMU_UART5CLK, 16, 1),
OWL_MUX_HW(CMU_UART6CLK, 16, 1),
OWL_MUX_HW(CMU_VCECLK, 4, 2),
OWL_MUX_HW(CMU_VDECLK, 4, 2),