OWL_FACTOR_HW
.factor_hw = OWL_FACTOR_HW(_reg, _shift, \
OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table),
OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table),
OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
OWL_FACTOR_HW(CMU_DECLK, 0, 3, 0, de_factor_table),
OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, hde_factor_table),
OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table),
OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table),
OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, hde_factor_table),
OWL_FACTOR_HW(CMU_LCDCLK, 0, 9, 0, lcd_factor_table),
OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table),
OWL_FACTOR_HW(CMU_BUSCLK, 12, 3, 0, dmm_factor_table),
OWL_FACTOR_HW(CMU_EDPCLK, 16, 3, 0, bisp_factor_table),
OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, bisp_factor_table),
OWL_FACTOR_HW(CMU_GPU3DCLK, 16, 3, 0, bisp_factor_table),
OWL_FACTOR_HW(CMU_GPU3DCLK, 24, 3, 0, bisp_factor_table),
OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, bisp_factor_table),
OWL_FACTOR_HW(CMU_IMXCLK, 0, 3, 0, bisp_factor_table),
OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
OWL_FACTOR_HW(CMU_SD3CLK, 0, 9, 0, sd_factor_table),
OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table),
OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table),