OV5_FEAT
.byte2 = OV5_FEAT(OV5_LPAR) | OV5_FEAT(OV5_SPLPAR) | OV5_FEAT(OV5_LARGE_PAGES) |
OV5_FEAT(OV5_DRCONF_MEMORY) | OV5_FEAT(OV5_DONATE_DEDICATE_CPU) |
OV5_FEAT(OV5_MSI),
OV5_FEAT(OV5_CMO) | OV5_FEAT(OV5_XCMO),
.associativity = OV5_FEAT(OV5_FORM1_AFFINITY) | OV5_FEAT(OV5_PRRN) |
OV5_FEAT(OV5_FORM2_AFFINITY),
.bin_opts = OV5_FEAT(OV5_RESIZE_HPT) | OV5_FEAT(OV5_HP_EVT),
.platform_facilities = OV5_FEAT(OV5_PFO_HW_RNG) | OV5_FEAT(OV5_PFO_HW_ENCR) | OV5_FEAT(OV5_PFO_HW_842),
.byte22 = OV5_FEAT(OV5_DRMEM_V2) | OV5_FEAT(OV5_DRC_INFO),
case OV5_FEAT(OV5_MMU_DYNAMIC):
case OV5_FEAT(OV5_MMU_EITHER): /* Either Available */
case OV5_FEAT(OV5_MMU_RADIX): /* Only Radix */
case OV5_FEAT(OV5_MMU_HASH):
case OV5_FEAT(OV5_XIVE_EITHER): /* Either Available */
case OV5_FEAT(OV5_XIVE_EXPLOIT): /* Only Exploitation mode */
case OV5_FEAT(OV5_XIVE_LEGACY): /* Only Legacy mode */
prom_parse_mmu_model(val & OV5_FEAT(OV5_MMU_SUPPORT), support);
if (val & OV5_FEAT(OV5_RADIX_GTSE))
prom_parse_xive_model(val & OV5_FEAT(OV5_XIVE_SUPPORT),
ibm_architecture_vec.vec5.mmu = OV5_FEAT(OV5_MMU_RADIX);
OV5_FEAT(OV5_RADIX_GTSE);
ibm_architecture_vec.vec5.mmu = OV5_FEAT(OV5_MMU_HASH);
ibm_architecture_vec.vec5.intarch = OV5_FEAT(OV5_XIVE_EXPLOIT);
OV5_FEAT(OV5_MMU_SUPPORT);
if (mmu_supported == OV5_FEAT(OV5_MMU_RADIX)) {
OV5_FEAT(OV5_RADIX_GTSE))) {
} else if (mmu_supported == OV5_FEAT(OV5_MMU_HASH)) {
feat = OV5_FEAT(vec5_fw_features_table[i].feature);
val = *vec5_xive & OV5_FEAT(OV5_XIVE_SUPPORT);
case OV5_FEAT(OV5_XIVE_EITHER):
case OV5_FEAT(OV5_XIVE_LEGACY):
case OV5_FEAT(OV5_XIVE_EXPLOIT):