drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2669

enum optc_dsc_mode optc_dsc_mode = OPTC_DSC_DISABLED;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3699

enum optc_dsc_mode dsc_mode = OPTC_DSC_DISABLED;

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

401

REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

363

REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1);

drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c

476

enum optc_dsc_mode dsc_mode = OPTC_DSC_DISABLED;

drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c

496

if (dsc_mode != OPTC_DSC_DISABLED) {

drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c

488

enum optc_dsc_mode dsc_mode = OPTC_DSC_DISABLED;

drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c

501

case OPTC_DSC_DISABLED:

drivers/gpu/drm/amd/display/dc/hpo/dcn401/dcn401_hpo_frl_stream_encoder.c

523

if (dsc_mode != OPTC_DSC_DISABLED) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1977

tg->funcs->set_dsc_config(tg, OPTC_DSC_DISABLED, 0, 0);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1983

se->funcs->dp_set_dsc_config(se, OPTC_DSC_DISABLED, 0, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

555

OPTC_DSC_DISABLED, 0, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

137

OPTC_DSC_DISABLED, 0, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1107

OPTC_DSC_DISABLED, 0, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

395

OPTC_DSC_DISABLED, 0, 0);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

818

OPTC_DSC_DISABLED, 0, 0);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

832

OPTC_DSC_DISABLED, 0, 0);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

193

if (dsc_mode != OPTC_DSC_DISABLED