Symbol: OTG
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
101
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
102
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
103
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 4, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
104
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 5, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
105
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
106
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
107
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 4, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
108
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 5, mask_sh)
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
116
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
117
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
118
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
119
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh)
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
38
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
39
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
51
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
52
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
53
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
54
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5)
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
86
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
87
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
88
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
89
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
35
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
36
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
37
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
38
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\
drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
38
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
39
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1)
drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
59
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
60
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
61
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
62
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
116
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
117
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
118
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
119
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
120
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
121
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
122
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
123
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
124
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
125
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
126
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
127
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
128
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
129
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
130
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
131
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
132
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
133
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
134
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
135
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
47
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
48
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
49
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
50
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
113
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
114
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
115
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
116
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
117
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
118
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
119
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
120
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
121
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
122
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
123
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
124
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
125
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
126
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
127
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
128
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
52
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
53
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
54
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
55
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
80
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
81
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
82
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
83
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
84
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
85
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
86
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
87
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
88
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
89
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
90
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
91
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
92
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
93
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
94
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
95
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
103
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
104
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
105
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
106
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
107
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
108
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
109
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
110
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
111
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
112
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
113
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
114
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
115
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
116
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
117
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
118
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
128
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
129
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
130
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
131
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
108
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
109
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
110
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
111
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
112
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
113
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
114
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
115
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
77
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
78
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
79
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
80
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
81
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
82
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
83
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
84
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
100
SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
101
SRII(PIXEL_RATE_CNTL, OTG, 3)
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
113
SRII(PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
114
SRII(PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
115
SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
116
SRII(PIXEL_RATE_CNTL, OTG, 3)
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
128
SRII(PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
129
SRII(PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
130
SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
131
SRII(PIXEL_RATE_CNTL, OTG, 3)
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
145
SRII(PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
146
SRII(PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
147
SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
148
SRII(PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
149
SRII(PIXEL_RATE_CNTL, OTG, 4)
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
157
SRII(PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
158
SRII(PIXEL_RATE_CNTL, OTG, 1)
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
184
SRII(PIXEL_RATE_CNTL, OTG, 0), \
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
185
SRII(PIXEL_RATE_CNTL, OTG, 1), \
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
186
SRII(PIXEL_RATE_CNTL, OTG, 2), \
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
187
SRII(PIXEL_RATE_CNTL, OTG, 3)
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
72
SRII(PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
73
SRII(PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
74
SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
75
SRII(PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
76
SRII(PIXEL_RATE_CNTL, OTG, 4),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
77
SRII(PIXEL_RATE_CNTL, OTG, 5)
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
85
SRII(PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
86
SRII(PIXEL_RATE_CNTL, OTG, 1)
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
98
SRII(PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
99
SRII(PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
224
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
225
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
226
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
227
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
258
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
259
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
260
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
261
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
262
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
263
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
323
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
324
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
325
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
326
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
373
HWSEQ_PIXEL_RATE_REG_LIST_201(OTG), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
374
HWSEQ_PHYPLL_REG_LIST_201(OTG), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
397
HWSEQ_PIXEL_RATE_REG_LIST_3(OTG), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
398
HWSEQ_PHYPLL_REG_LIST_3(OTG), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
428
SRII(PIXEL_RATE_CNTL, OTG, 0), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
429
SRII(PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
430
SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
431
SRII(PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
432
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
433
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
434
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
435
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
483
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
484
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
485
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
486
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
487
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
538
HWSEQ_PIXEL_RATE_REG_LIST_302(OTG), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
539
HWSEQ_PHYPLL_REG_LIST_302(OTG), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
546
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
547
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
567
HWSEQ_PIXEL_RATE_REG_LIST_303(OTG), \
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
568
HWSEQ_PHYPLL_REG_LIST_303(OTG), \
drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
217
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
225
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
233
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
222
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
230
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
238
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
166
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
177
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
184
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
192
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
244
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
252
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
260
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
251
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
259
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
274
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
240
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
248
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
256
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
164
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
172
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
180
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
239
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
247
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
255
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
241
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
249
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
257
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
246
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
254
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
262
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
247
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
257
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
265
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
272
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
279
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
232
IRQ_REG_ENTRY(DC_IRQ_SOURCE_VUPDATE1, OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
238
IRQ_REG_ENTRY(DC_IRQ_SOURCE_VBLANK1, OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
244
IRQ_REG_ENTRY(DC_IRQ_SOURCE_DC1_VLINE0, OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
211
IRQ_REG_ENTRY(DC_IRQ_SOURCE_VUPDATE1, OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
217
IRQ_REG_ENTRY(DC_IRQ_SOURCE_VBLANK1, OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
223
IRQ_REG_ENTRY(DC_IRQ_SOURCE_DC1_VLINE0, OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
210
IRQ_REG_ENTRY(DC_IRQ_SOURCE_VUPDATE1, OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
216
IRQ_REG_ENTRY(DC_IRQ_SOURCE_VBLANK1, OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
222
IRQ_REG_ENTRY(DC_IRQ_SOURCE_DC1_VLINE0, OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
227
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
237
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
245
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
252
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
259
IRQ_REG_ENTRY(OTG, reg_num,\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
101
SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
102
SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
103
SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
104
SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst)
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
35
SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
36
SRI(OTG_VUPDATE_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
37
SRI(OTG_VREADY_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
38
SRI(OTG_BLANK_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
39
SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
40
SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
41
SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
42
SRI(OTG_H_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
43
SRI(OTG_H_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
44
SRI(OTG_H_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
45
SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
46
SRI(OTG_H_TIMING_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
47
SRI(OTG_V_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
48
SRI(OTG_V_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
49
SRI(OTG_V_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
50
SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
51
SRI(OTG_INTERLACE_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
52
SRI(OTG_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
53
SRI(OTG_STEREO_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
54
SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
55
SRI(OTG_STEREO_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
56
SRI(OTG_V_TOTAL_MAX, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
57
SRI(OTG_V_TOTAL_MID, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
58
SRI(OTG_V_TOTAL_MIN, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
59
SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
60
SRI(OTG_TRIGA_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
61
SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
62
SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
63
SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
64
SRI(OTG_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
65
SRI(OTG_STATUS_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
66
SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
67
SRI(OTG_BLACK_COLOR, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
68
SRI(OTG_CLOCK_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
69
SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
70
SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
71
SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
72
SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
73
SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
74
SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
79
SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
80
SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
81
SRI(OTG_GSL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
82
SRI(OTG_CRC_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
83
SRI(OTG_CRC0_DATA_RG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
84
SRI(OTG_CRC0_DATA_B, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
85
SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
86
SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
87
SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
88
SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
89
SRI(OTG_CRC1_DATA_RG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
90
SRI(OTG_CRC1_DATA_B, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
91
SRI(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
92
SRI(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
93
SRI(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
94
SRI(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
96
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
97
SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst)
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
33
SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
34
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
35
SRI(OTG_GSL_WINDOW_X, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
36
SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
37
SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
38
SRI(OTG_DSC_START_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
39
SRI(OTG_CRC_CNTL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
45
SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
46
SRI(OTG_DRR_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
47
SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst)
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
33
SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
34
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
35
SRI(OTG_GSL_WINDOW_X, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
36
SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
37
SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
38
SRI(OTG_DSC_START_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
100
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
101
SRI(OTG_GSL_WINDOW_X, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
102
SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
103
SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
104
SRI(OTG_DSC_START_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
105
SRI(OTG_CRC_CNTL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
106
SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
107
SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
113
SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst)
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
34
SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
35
SRI(OTG_VUPDATE_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
36
SRI(OTG_VREADY_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
37
SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
38
SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
39
SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
40
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
41
SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
42
SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
43
SRI(OTG_H_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
44
SRI(OTG_H_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
45
SRI(OTG_H_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
46
SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
47
SRI(OTG_H_TIMING_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
48
SRI(OTG_V_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
49
SRI(OTG_V_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
50
SRI(OTG_V_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
51
SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
52
SRI(OTG_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
53
SRI(OTG_STEREO_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
54
SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
55
SRI(OTG_STEREO_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
56
SRI(OTG_V_TOTAL_MAX, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
57
SRI(OTG_V_TOTAL_MIN, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
58
SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
60
SRI(OTG_TRIGA_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
61
SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
62
SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
63
SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
64
SRI(OTG_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
65
SRI(OTG_STATUS_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
66
SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
67
SRI(OTG_BLANK_DATA_COLOR, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
68
SRI(OTG_BLANK_DATA_COLOR_EXT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
69
SRI(OTG_M_CONST_DTO0, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
70
SRI(OTG_M_CONST_DTO1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
71
SRI(OTG_CLOCK_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
72
SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
73
SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
74
SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
75
SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
76
SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
77
SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
82
SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
83
SRI(OTG_GSL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
84
SRI(OTG_CRC_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
85
SRI(OTG_CRC_CNTL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
86
SRI(OTG_CRC0_DATA_RG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
87
SRI(OTG_CRC0_DATA_B, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
88
SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
89
SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
90
SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
91
SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
93
SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
94
SRI(OTG_DRR_CONTROL, OTG, inst)
drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
99
SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
100
SRI(OTG_CRC_CNTL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
102
SRI(OTG_DRR_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
103
SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
104
SRI(INTERRUPT_DEST, OTG, inst)
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
32
SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
33
SRI(OTG_VUPDATE_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
34
SRI(OTG_VREADY_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
35
SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
36
SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
37
SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
38
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
39
SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
40
SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
41
SRI(OTG_H_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
42
SRI(OTG_H_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
43
SRI(OTG_H_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
44
SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
45
SRI(OTG_H_TIMING_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
46
SRI(OTG_V_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
47
SRI(OTG_V_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
48
SRI(OTG_V_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
49
SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
50
SRI(OTG_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
51
SRI(OTG_STEREO_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
52
SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
53
SRI(OTG_STEREO_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
54
SRI(OTG_V_TOTAL_MAX, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
55
SRI(OTG_V_TOTAL_MIN, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
56
SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
57
SRI(OTG_TRIGA_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
58
SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
59
SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
60
SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
61
SRI(OTG_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
62
SRI(OTG_STATUS_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
63
SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
64
SRI(OTG_M_CONST_DTO0, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
65
SRI(OTG_M_CONST_DTO1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
66
SRI(OTG_CLOCK_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
67
SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
68
SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
69
SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
70
SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
71
SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
72
SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
77
SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
78
SRI(OTG_GSL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
79
SRI(OTG_CRC_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
80
SRI(OTG_CRC0_DATA_RG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
81
SRI(OTG_CRC0_DATA_B, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
82
SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
83
SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
84
SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
85
SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
87
SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
88
SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
89
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
90
SRI(OTG_GSL_WINDOW_X, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
91
SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
92
SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
93
SRI(OTG_DSC_START_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
94
SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
95
SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
101
SRI(OTG_DRR_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
102
SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
103
SRI(INTERRUPT_DEST, OTG, inst)
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
33
SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
34
SRI(OTG_VUPDATE_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
35
SRI(OTG_VREADY_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
36
SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
37
SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
38
SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
39
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
40
SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
41
SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
42
SRI(OTG_H_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
43
SRI(OTG_H_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
44
SRI(OTG_H_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
45
SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
46
SRI(OTG_H_TIMING_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
47
SRI(OTG_V_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
48
SRI(OTG_V_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
49
SRI(OTG_V_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
50
SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
51
SRI(OTG_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
52
SRI(OTG_STEREO_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
53
SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
54
SRI(OTG_STEREO_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
55
SRI(OTG_V_TOTAL_MAX, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
56
SRI(OTG_V_TOTAL_MIN, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
57
SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
58
SRI(OTG_TRIGA_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
59
SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
60
SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
61
SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
62
SRI(OTG_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
63
SRI(OTG_STATUS_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
64
SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
65
SRI(OTG_M_CONST_DTO0, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
66
SRI(OTG_M_CONST_DTO1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
67
SRI(OTG_CLOCK_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
68
SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
69
SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
70
SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
71
SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
72
SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
73
SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
78
SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
79
SRI(OTG_GSL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
80
SRI(OTG_CRC_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
81
SRI(OTG_CRC0_DATA_RG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
82
SRI(OTG_CRC0_DATA_B, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
83
SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
84
SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
85
SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
86
SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
88
SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
89
SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
90
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
91
SRI(OTG_GSL_WINDOW_X, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
92
SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
93
SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
94
SRI(OTG_DSC_START_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
95
SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
96
SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
690
SRII(PIXEL_RATE_CNTL, OTG, 0), \
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
691
SRII(PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
692
SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
693
SRII(PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
694
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
695
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
696
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
697
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
697
SRII(PIXEL_RATE_CNTL, OTG, 0), \
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
698
SRII(PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
699
SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
700
SRII(PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
701
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
702
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
703
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
704
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
689
SRII(PIXEL_RATE_CNTL, OTG, 0), \
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
690
SRII(PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
691
SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
692
SRII(PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
693
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
694
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
695
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
696
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
684
SRII(PIXEL_RATE_CNTL, OTG, 0), \
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
685
SRII(PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
686
SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
687
SRII(PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
688
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
689
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
690
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
691
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
541
SRII(PIXEL_RATE_CNTL, OTG, 0), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
542
SRII(PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
543
SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
544
SRII(PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
545
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
546
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
547
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
548
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1003
SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1004
SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1005
SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1006
SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1007
SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1008
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1009
SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1010
SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1011
SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1012
SRI_ARR(OTG_H_TOTAL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1013
SRI_ARR(OTG_H_BLANK_START_END, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1014
SRI_ARR(OTG_H_SYNC_A, OTG, inst), SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1015
SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1016
SRI_ARR(OTG_V_BLANK_START_END, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1017
SRI_ARR(OTG_V_SYNC_A, OTG, inst), SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1018
SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1019
SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1020
SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1021
SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1022
SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1023
SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1024
SRI_ARR(OTG_TRIGA_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1025
SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1026
SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1027
SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1028
SRI_ARR(OTG_STATUS, OTG, inst), SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1029
SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1030
SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1031
SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1032
SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1033
SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1034
SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1035
SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1036
SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1037
SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1038
SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1042
SRI_ARR(CONTROL, VTG, inst), SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1043
SRI_ARR(OTG_GSL_CONTROL, OTG, inst), SRI_ARR(OTG_CRC_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1044
SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1045
SRI_ARR(OTG_CRC0_DATA_B, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1046
SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1047
SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1048
SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1049
SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1051
SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1052
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1053
SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1054
SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1055
SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1056
SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1057
SRI_ARR(OTG_DSC_START_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1058
SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1059
SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1064
SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1065
SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1066
SRI_ARR(INTERRUPT_DEST, OTG, inst)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1249
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
1250
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
208
SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 0, index), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
209
SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 1, index), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
210
SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 2, index), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
211
SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 3, index)
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
537
SRII(PIXEL_RATE_CNTL, OTG, 0), \
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
538
SRII(PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
539
SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
540
SRII(PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
541
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
542
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
543
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
544
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
174
SRII(PIXEL_RATE_CNTL, OTG, 0), \
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
175
SRII(PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
176
SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
177
SRII(PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
178
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
179
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
180
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
181
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
219
SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
220
SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
221
SRI_ARR(OTG_VREADY_PARAM, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
222
SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
223
SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
224
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
225
SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
226
SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
227
SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
228
SRI_ARR(OTG_H_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
229
SRI_ARR(OTG_H_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
230
SRI_ARR(OTG_H_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
231
SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
232
SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
233
SRI_ARR(OTG_V_TOTAL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
234
SRI_ARR(OTG_V_BLANK_START_END, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
235
SRI_ARR(OTG_V_SYNC_A, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
236
SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
237
SRI_ARR(OTG_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
238
SRI_ARR(OTG_STEREO_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
239
SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
240
SRI_ARR(OTG_STEREO_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
241
SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
242
SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
243
SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
244
SRI_ARR(OTG_V_COUNT_STOP_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
245
SRI_ARR(OTG_V_COUNT_STOP_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
246
SRI_ARR(OTG_TRIGA_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
247
SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
248
SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
249
SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
250
SRI_ARR(OTG_STATUS, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
251
SRI_ARR(OTG_STATUS_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
252
SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
253
SRI_ARR(OTG_M_CONST_DTO0, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
254
SRI_ARR(OTG_M_CONST_DTO1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
255
SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
256
SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
257
SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
258
SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
259
SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
260
SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
261
SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
266
SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
267
SRI_ARR(OTG_GSL_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
268
SRI_ARR(OTG_CRC_CNTL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
269
SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
270
SRI_ARR(OTG_CRC0_DATA_B, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
271
SRI_ARR(OTG_CRC1_DATA_RG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
272
SRI_ARR(OTG_CRC1_DATA_B, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
273
SRI_ARR(OTG_CRC2_DATA_RG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
274
SRI_ARR(OTG_CRC2_DATA_B, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
275
SRI_ARR(OTG_CRC3_DATA_RG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
276
SRI_ARR(OTG_CRC3_DATA_B, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
277
SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
278
SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
279
SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
280
SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
281
SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
282
SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
283
SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
284
SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
285
SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
286
SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
287
SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
288
SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
289
SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
290
SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
291
SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
292
SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
294
SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
295
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
296
SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
297
SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
298
SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
299
SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
300
SRI_ARR(OTG_DSC_START_POSITION, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
301
SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
302
SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
307
SRI_ARR(OTG_DRR_CONTROL, OTG, inst),\
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
309
SRI_ARR(INTERRUPT_DEST, OTG, inst)
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
35
SRII(PIXEL_RATE_CNTL, OTG, 0), \
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
36
SRII(PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
37
SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
38
SRII(PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
39
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
40
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
41
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.h
42
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
516
SRII(PIXEL_RATE_CNTL, OTG, 0), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
517
SRII(PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
518
SRII(PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
519
SRII(PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
520
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
521
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
522
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
523
SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
483
SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
484
SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
485
SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
486
SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
487
SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
488
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
489
SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
490
SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
491
SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
492
SRI_ARR(OTG_H_TOTAL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
493
SRI_ARR(OTG_H_BLANK_START_END, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
494
SRI_ARR(OTG_H_SYNC_A, OTG, inst), SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
495
SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
496
SRI_ARR(OTG_V_BLANK_START_END, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
497
SRI_ARR(OTG_V_SYNC_A, OTG, inst), SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
498
SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
499
SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
500
SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
501
SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
502
SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
503
SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
504
SRI_ARR(OTG_TRIGA_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
505
SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
506
SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
507
SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
508
SRI_ARR(OTG_STATUS, OTG, inst), SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
509
SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
510
SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
511
SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
512
SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
513
SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
514
SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
515
SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
516
SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
517
SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
518
SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
522
SRI_ARR(CONTROL, VTG, inst), SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
523
SRI_ARR(OTG_GSL_CONTROL, OTG, inst), SRI_ARR(OTG_CRC_CNTL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
524
SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
525
SRI_ARR(OTG_CRC0_DATA_B, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
526
SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
527
SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
528
SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
529
SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
531
SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
532
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
533
SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
534
SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
535
SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
536
SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
537
SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
538
SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
544
SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
545
SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
546
SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
547
SRI_ARR(INTERRUPT_DEST, OTG, inst)
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
634
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
635
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3), \
drivers/regulator/qcom_spmi-regulator.c
1642
SPMI_VREG_VS(OTG, 0, INF),